MESI_CMP_directory-dir.sm: directory controller.MESI_CMP_directory-L2cache.sm: L2 cache controller.MESI_CMP_directory-L1cache.sm: L1 cache controller.Optimization helps reducing write-back traffic to the L2 cache This means that cache blocks which have notīeen written to and has readable permission only can drop the cacheīlock from the private L1 cache without informing the L2 cache. The protocol supports silent eviction of clean cache blocks from.when aĬache block is writable but not yet written). Same core soon and thus save an extra request with this In anticipation that a cache blocks read would be written by the One of the primary optimizations in this protocol is that if a L1Ĭache request a data block even for read permission, the L2 cacheĬontroller if finds that no other core has the block, it returns theĬache block with exclusive permission.DMA controller is responsible for satisfying coherent The Directory controller acts as interface to the MemoryĬontroller/Off-chip main memory and is also responsible for coherenceĪcross multiple chips/and external coherence request from DMAĬontroller. Maintaining coherence of on-chip data through directory coherence L2 cacheĬontroller is responsible for managing the shared L2 cache and for Number of instantiations of L1 cache controller isĮqual to the number of cores in the simulated system. L1 cache controller is responsible for managing L1 Instruction and L2 cache controller, Directory controller and DMA controller. The protocol has four types of controllers – L1 cache controller,.With the corresponding cache blocks in the shared L2 cache. The on-chip cache coherence is maintained through DirectoryĬoherence scheme, where the directory information is co-located.State means the cache block is only readable and possible multipleĬopies of it exists in multiple private cache and as well as in the E state represent a cache block withĮxclusive permission (i.e. has exclusive permission) and has been dirtied (i.e. A block in M state means the blocks is writable At high level the protocol has four stable states, M, E,.Inclusion is maintained between the L1 and L2 cache.L1Ĭache is split into Instruction and Data cache.
Private to a core, while the L2 cache is shared among the cores. This protocol models two-level cache hierarchy.
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